1. Field of the Invention
The present invention relates to a semiconductor memory device and, more specifically, to a dynamic type memory or a dynamic RAM (DRAM) capable of transferring data at high speed through an input/output path.
2. Description of the Related Art
In a dynamic type memory, a divided cell array operating system is employed wherein a memory cell array is divided into a plurality of cell arrays (sub arrays) and some of the cell arrays are operated at the same time. This system makes it possible to reduce a charge/discharge current of bit lines which occupies a large part of the consumed current in an operation of rows. The number of sub arrays has a close relation to the operation speed of the memory. If each sub array is large in size, the capacity of word lines is increased too much and thus the rise and fall speeds of the word lines are decreased. Since the capacity of bit lines is also increased too much, a difference in potential between a pair of bit lines is lessened, and the speed at which the potential difference is amplified by a sense amplifier becomes slow, with the result that the operation speed of the entire memory is decreased. For this reason, as the memory is miniaturized and its capacity is increased, the number of sub arrays is likely to increase in order to reduce the charge/discharge current of the bit lines and then prevent the operation speed of the entire memory from lowering.
A dynamic RAM (DRAM) is achieved at low cost as a memory which is employed in bulk in a computer system. In the field of computers, the operation speed of a microprocessor (MPU) is remarkably improved and thus becomes higher and higher than that of the DRAM. The improvement in speed of data transfer between the MPU and DRAM is an important factor in increasing the processing speed of the total computer system. Various improvements have been made to increase the data transfer speed, and a typical one of them is to adopt a high-speed memory or a cache memory. The memory, which is interposed between the MPU and the main memory to shorten the difference between the cycle time of the MPU and the access time of the main memory, improves in efficiency in use of the MPU.
As examples of the cache memory, there are a static RAM (SRAM) of a chip separated from both a MPU chip and a DRAM chip, an SRAM called an on-chip cache memory or an embedded memory mounted on an MPU chip (an MPU chip mounted with a cache memory may have an SRAM cache memory of another chip), and an SRAM cell mounted on a DRAM chip.
The technique of mounting a cache memory including SRAM cells on a DRAM chip, is disclosed in "A Circuit Design of Intelligent CDDRAM with Automatic Write Back Capability," 1990 Symposium on VLSI Circuits, Digest of Technical Papers, pp 79-80. According to this technique, an SRAM cell is added to each column of a DRAM using cells each having one transistor and one capacitor, and this SRAM cell is employed as a cache memory. Moreover, when data of an address to be accessed is not stored in the cache memory (mishit), the data of the cache memory is written back to a DRAM cell corresponding to the address, and then data stored in a DRAM cell of an address to be accessed are read out into the cache memory. This cache memory mounted DRAM can be employed together with a cache memory mounted MPU.
The technique of using sense amplifiers of bit lines of a DRAM as cache memories is disclosed in Japanese Patent Application No. 3-41316 (Jpn. Pat. Appln. KOKAI Publication No. 4-212780) whose applicant is the same as that of the present application. A specific constitution of the cache memories and a specific control operation thereof are disclosed in Japanese Patent Application No. 3-41315 whose applicant is also the same as that of the present application.
Furthermore, Japanese Patent Application No. 4-131095, the applicant of which is the same as that of the present application, proposes a DRAM wherein a memory region is divided into a plurality of sub arrays, the sub arrays are operated independently of one another, and sense amplifiers of bit lines are employed as cache memories, thereby enhancing the hit rate of the cache memories.
Since, in this DRAM, a sense amplifier holds data read out from a row corresponding to each of different addresses for each of the sub arrays, a hit possibility of requesting access to a selected row can be increased, and the average of data access time, which depends on both the hit possibility and mishit possibility of not requesting the access, can be reduced.
A cache memory system using sense amplifiers will now be described in brief. Assume that a DRAM stands by for access from an MPU and, in this case, data read out from memory cells of a row address is latched in the sense amplifiers.
If, there is access to the row address, data of whose memory cells is latched in the sense amplifiers (hit), the data can be output only by the operation of columns without that of rows, and access time necessary for the operation of rows can be shortened accordingly.
In contrast, if there is access to a row address, data of whose memory cells is not latched in the sense amplifiers (mishit), it is necessary that the data of the sense amplifiers is written back to the memory cells (or the sense amplifiers are equalized), and then data of a new row address be latched in the sense amplifiers. In this mishit case, the access time is much longer than when no cache memory system is employed.
If the hit rate of the cache memories is low, the average access time of the system is lengthened. To increase the hit rate is therefore important for shortening the average access time of the system.
In order to enhance the foregoing hit rate, there is a first method of increasing the capacity of each of the cache memories or a second method of dividing the cache memories into some banks.
If the first method is applied to the cache memory system using sense amplifiers, the sense amplifiers, which stand by for access while latching data, are increased in number. Generally, as described above, a large-capacity memory performs partial activation of activating some of sub arrays at the same time and, in this case, no data is usually held in the sense amplifiers related to the sub arrays in which an operation of rows is not performed. If, however, these sense amplifiers are caused to latch data, the sense amplifiers standing by for access while latching data, can be increased in number, as can be the capacity of the cache memories, thereby enhancing the hit rate.
If the above second method is applied to the cache memory system using sense amplifiers, these sense amplifiers are divided into a plurality of banks. In a versatile DRAM, generally, the sense amplifiers related to a plurality of sub arrays operate simultaneously to perform sensing, latching, and equalizing operations at the same timing, while the sense amplifiers related to the sub arrays in which an operation of rows is not performed, as described above, are allowed to stand by while latching data. The simultaneously-operating sense amplifiers are called banks. In order to divide 10 the sense amplifiers into banks for the purpose of increasing the hit rate of the cache memories, the following conditions are required:
(1) Each bank has independent sense amplifiers. PA1 (2) The sense amplifiers of a bank, in which an operation of rows is not performed, are able to continue latching data of the bank, irrespective of row addresses of the other banks. PA1 (3) Each bank includes data paths corresponding to all I/O pads since a specific bank is accessed to access a certain cache memory, whereas in a multi-bit DRAM, data has to be supplied from the accessed bank to the I/O pads at the same timing. PA1 a plurality of memory cell blocks arranged in a second direction on a semiconductor chip, each constituting a memory cell bank and including a plurality of sub arrays in a form of division of a memory cell array and a plurality of sense amplifiers used as cache memories, the sub arrays and the sense amplifiers being alternately arranged in a first direction perpendicular to the second direction, with one of the sense amplifiers being on each end of an arrangement of the sub arrays and the sense amplifiers, each of the sub arrays having a plurality of dynamic type memory cells arranged in a matrix, a plurality of word lines each connected to those of the memory cells which are in a row and a plurality of bit lines each connected to those of the memory cells which are in a column, each of the sense amplifiers including a plurality of amplifier circuits connected to the bit lines, each of the amplifier circuits for sensing and amplifying a potential read out from a memory cell when a corresponding bit line is selected; PA1 a plurality of data lines provided to the sub arrays, the data lines being arranged on the semiconductor chip and extending in the second direction, each of the data lines for transferring data sensed and amplified by an amplifier circuit of a sense amplifier of a corresponding sub array, the bit line connected to which amplifier circuit is selected; and PA1 a plurality of input/output pads provided to the sub arrays of the banks, the input/output pads being in an arrangement in the first direction on the semiconductor chip, the arrangement being located in one side of the memory cell array.
A shared sense amplifier configuration is known to reduce the area of a memory chip. In this system, as shown in FIG. 4, a sense amplifier 62 constituted of sensing NMOS transistors and restoring PMOS transistors is provided between two sub arrays 61, and the two sub arrays 61 are selectively connected to the single sense amplifier 62 by controlling data transfer transistors in response to control signals Xfer1 and Xfer2, thereby time-divisionally using the single sense amplifier 62 by the two sub arrays 61.
The above shared sense amplifier configuration has been actually adopted in a large-capacity memory such as a 16-Mbit memory to decrease the chip area. The efficiency in configuration in this system will now be 10 described with reference to schematic views of FIGS. 5 and 6.
The configuration shown in FIG. 5 is more efficient than that shown in FIG. 6. More specifically, since the configuration of FIG. 6 includes contiguous sense amplifiers 72, the number of sense amplifiers in FIG. 6 is larger than that of sense amplifiers in FIG. 5, with the result that the chip area is increased and the configuration efficiency is lowered.
If the cache memory system using the sense amplifiers is applied to the configuration shown in FIG. 5 to increase the capacity of the cache memory, the configuration as shown in FIG. 7 is obtained. More specifically, half the sub arrays 71 (A, B, C) or 71 (a, b, c) are activated, and data is latched by sense amplifiers 72 excluding a sense amplifier at one end of the configuration in FIG. 7, thereby increasing the number of sense amplifiers which stand by for access while latching the data.
In the shared sense amplifier configuration shown in FIG. 7, however, the sub arrays A and a cannot be divided into different banks since the foregoing condition (1) is not satisfied, nor can be the sub arrays a and B since they share a sense amplifier with each other and thus the condition (1) is not satisfied. It is thus understood that in the shared sense amplifier configuration as shown in FIG. 7, the sub arrays cannot be divided into banks.
In other words, the sub arrays have to be separate in order to group the sub arrays into banks in the shared sense amplifier configuration. This lessens the effect of reduction in chip area due to high configuration efficiency which is advantageous to the shared sense amplifier configuration.
If an array is divided into sub arrays in its lateral direction, as in the conventional case, and the sub arrays are separate to group the sub arrays into two banks 1 and 2, a shared sense amplifier configuration shown in FIG. 8 is obtained.
The configuration shown in FIG. 8 employs a vertical surface mounting package (VSMP) in which all I/O pads 76 for inputting/outputting data having bit number corresponding to a bit configuration are collectively provided on one side of the array of the sub arrays and vertically mounted on a memory chip mounting printed circuit board. By using the VSMP, a lead frame inside the package and wires on the circuit board can be shortened and thus data can be transferred at high speed.
In the configuration shown in FIG. 8, data lines 73 are provided for each of sub arrays 71 and connected to a data buffer (DQ buffer) 74 corresponding to each of the sub arrays. Each multiplexer (MPX) 75 is 10 connected to corresponding data buffers 74 of the banks 1 and 2. The number of multiplexers 75 is equal to that of I/O pads 76.
If the configuration shown in FIG. 8 becomes larger and larger, both the sub arrays 71 and sense amplifiers 72 are increased in number. This may cause a problem, taking into consideration that the sub arrays are likely to increase in number as the DRAM increases in capacity as described above. The problem is that data paths for connecting the DQ buffers 74 and multiplexers 75 are lengthened thereby to prevent data from being transferred at high speed in the memory chip.
As described above, the conventional DRAM has the problem wherein a long data path prevents high-speed data transfer if the cache memories are increased in number and divided into plural banks in order to enhance the hit rate of the cache memories in the shared sense amplifier configuration with high configuration efficiency.
In the conventional DRAM, the enhancement of the hit rate and the high-speed data transfer are incompatible to achieve the shared sense amplifier configuration or the sense amplifier cache memory system in a small area.